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| author | Shagun Agrawal <agrawalshagun07@gmail.com> | 2024-08-18 21:04:35 +0530 |
|---|---|---|
| committer | Shagun Agrawal <agrawalshagun07@gmail.com> | 2024-08-18 21:04:35 +0530 |
| commit | f0b04ec099de12ae713e3a381d17b1af478f769a (patch) | |
| tree | 69115c714e099454eb448dbe9cc2184bc59af4f2 /src/cljcc/compiler.clj | |
| parent | 702daa89c7f451f01933e659b59a4daaa01f10ab (diff) | |
Add bitwise operators
Pass chapter 3 bitwise operators
Diffstat (limited to 'src/cljcc/compiler.clj')
| -rw-r--r-- | src/cljcc/compiler.clj | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/cljcc/compiler.clj b/src/cljcc/compiler.clj index cec875b..7d2a93b 100644 --- a/src/cljcc/compiler.clj +++ b/src/cljcc/compiler.clj @@ -83,7 +83,8 @@ src2 (tacky-val->assembly-operand (:src2 instruction)) dst (tacky-val->assembly-operand (:dst instruction)) div? (= binop :div) - mod? (= binop :mod)] + mod? (= binop :mod) + bit-shift? (contains? #{:bit-right-shift :bit-left-shift} binop)] (cond div? [(mov-instruction src1 (reg-operand :ax)) (cdq-instruction) @@ -93,6 +94,9 @@ (cdq-instruction) (idiv-instruction src2) (mov-instruction (reg-operand :dx) dst)] + bit-shift? [(mov-instruction src1 dst) + (mov-instruction src2 (reg-operand :cx)) + (binary-instruction binop (reg-operand :cl) dst)] :else [(mov-instruction src1 dst) (binary-instruction binop src2 dst)]))) (def tacky->assembly-transformers |