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authorShagun Agrawal <agrawalshagun07@gmail.com>2024-12-17 22:04:27 +0530
committerShagun Agrawal <agrawalshagun07@gmail.com>2024-12-17 22:04:27 +0530
commitb50b3552de7e0e6bf71d78e59adec5e305d7618b (patch)
tree26bc0d847254fe2ca6cf5af048e7db015478a8e9 /src/cljcc/schema.clj
parent6aa5955f791771533d7ff8ac4f7f7d99b6f91641 (diff)
Add code emission for unsigned int/long. Complete chapter 12
Diffstat (limited to 'src/cljcc/schema.clj')
-rw-r--r--src/cljcc/schema.clj16
1 files changed, 15 insertions, 1 deletions
diff --git a/src/cljcc/schema.clj b/src/cljcc/schema.clj
index 46aa316..23d7967 100644
--- a/src/cljcc/schema.clj
+++ b/src/cljcc/schema.clj
@@ -483,7 +483,7 @@
(def AssemblyType [:enum :longword :quadword])
-(def CondCode [:enum :e :ne :g :ge :l :le])
+(def CondCode [:enum :e :ne :g :ge :l :le :a :ae :b :be])
(def Register [:enum :ax :dx :di :si :r8 :r9 :r10 :r11 :cx :cl :sp])
@@ -567,6 +567,12 @@
[:assembly-type #'AssemblyType]
[:operand #'AssemblyOperand]])
+(def AssemblyDivInstruction
+ [:map
+ [:op [:= :div]]
+ [:assembly-type #'AssemblyType]
+ [:operand #'AssemblyOperand]])
+
(def AssemblyCmpInstruction
[:map
[:op [:= :cmp]]
@@ -602,14 +608,22 @@
[:src #'AssemblyOperand]
[:dst #'AssemblyOperand]])
+(def AssemblyMovZeroExtendInstruction
+ [:map
+ [:op [:= :mov-zero-extend]]
+ [:src #'AssemblyOperand]
+ [:dst #'AssemblyOperand]])
+
(def AssemblyInstruction
[:multi {:dispatch :op}
[:mov #'AssemblyMovInstruction]
[:movsx #'AssemblyMovsxInstruction]
+ [:mov-zero-extend #'AssemblyMovZeroExtendInstruction]
[:unary #'AssemblyUnaryInstruction]
[:binary #'AssemblyBinaryInstruction]
[:cmp #'AssemblyCmpInstruction]
[:idiv #'AssemblyIdivInstruction]
+ [:div #'AssemblyDivInstruction]
[:cdq #'AssemblyCdqInstruction]
[:jmp #'AssemblyJmpInstruction]
[:jmpcc #'AssemblyJmpCCInstruction]